The Web Site to Remember National Semiconductor's Series 32000 Family


Richard's coprocessor board was inspired by an article in the Byte magazine of August 1985. The article described in detail a PC add-on board based on a Series 32000 microprocessor: the Definicon DSI-32 coprocessor board. Richard was excited and began in 1986 to build an own version of this board. Luckily he was able to get most of the software (except the compilers) and the powerful second generation NS32332 CPU. Definicon has used the first generation NS32032 CPU.

The mentioned Byte article is available online at

Richard worked on the board for three years. In the 1980's PCB technology was difficult and expensive. Therefore the board was build with wire-wrap technology. To lower the design risks the operating frequency was limited to 5 MHz. Another reason was that a 10 MHz NS32081 FPU was expensive too. In the beginning the board used DRAM as main memory. But due to an unidentified bug the DRAM was taken off and SRAM was build in. Later Richard found out that the two-phase clock of the CPU was connected inverted. The density of the SRAM chips was 256 kbits and their package was a 28-pin DIP. The large package resulted in a space disadvantage compared to DRAM chips. To overcome this limitation Richard build small towers of four SRAM chips and used four towers for 512 kbytes of RAM. Instead of PALs electrically erasable GALs were used for the glue logic.

The final tests took place in 1989 on a PC-AT. After all the hard work it was a proud moment for Richard to see all tests passing without any error.

Fig. 1. Richard's coprocessor board with the SRAM towers at the right edge.

Around 2008 Richard decided to upgrade his board. The SRAM towers were not very reliable and cheap SRAMs were available with 4 Mbits density. Four of them were build in and make now 2 Mbytes of main memory. The next two photos show the board after the upgrade.

Fig. 2. Top view of Richard's coprocessor board after the SRAM upgrade.

Fig. 3. Bottom view of Richard's coprocessor board.

In September 2015 Richard and I tested the board again. We used a modern PC which has still two ISA slots. The operating system for the test was Windows 95. The next photo shows the PC with the installed coprocessor board.

Fig. 4. Richard's coprocessor board sitting in his host system.

The three screen shots below show that the old board is still fully functional. If you want more information about the software see Software/Definicon .

Fig. 5. The first test to run: the hardware test.

Fig. 6. A character based graphis test.

Fig. 7. The monitor program running in full screen mode.

In September 2017 Richard and I got access to the Greenhills compiler for the Definicon board. Our first goal was to compile the Dhrystone benchmark and let it run.

Fig. 8. The Dhrystone benchmark is now running. In the top right corner the compile command with the used options is shown.

The source code of Dhrystone contains a long list of systems which have been benchmarked. The following table only shows the entries for National Semiconductor and the new result of Richard.

Machine CPU Oper. Sys. Compiler Dhry. no Regs Dhrystone Regs
NSC ICM-3216NS32016-10MHzUNIX SVR2cc10411084
Sequent Balance 8000NS32032-10MHzDynix 2.0cc12501315
IBM PC/DSI-32NS32032-10MHzMSDOS 3.1GreenHills 2.1412821315
RichardNS32332 5MHzWindows 95GreenHills 2.14793 (1.1)-

The results in the table are for Dhrystone 1.0 except for Richard. Dhrystone 1.1 is a little slower. There will be new numbers in the near future. The NS32332 is obviously faster and clearly outperforms the first generation of CPUs.

If somebody wants to play with an old benchmark, here is the source code: dhrystone.c

This chapter was last modified on 17 December 2017. Next chapter: Sequent